1. Field of the Invention
The present invention generally relates to a half-rate clock and data recovery (CDR) circuit operating at a half rate of 5 GHz equal to a half of a full rate of 10 GHz and more particularly, to improvement of margin of high-speed operation of the half-rate CDR circuit.
2. Description of the Prior Art
Conventionally, in response to trends to higher speed of optical communication network, CDR circuits have been manufactured by a high-speed process of semiconductors, etc. so as to operate at a data transfer rate of not less than 10 Gbits/sec. (Gbps). However, in view of recent trends to lower power consumption, the CDR circuits are manufactured by a CMOS process. Generally, in the CMOS process, the CDR circuits are manufactured so as to operate at opposite clock edges such that a ratio of a cutoff frequency Ft to a maximum oscillation frequency Fmax in a transistor, i.e., (Ft/Fmax) is compensated for, so that the CDR circuits do not need to operate at high speed and thus, may operate at the half rate of 5 GHz.
As described in, for example, a paper entitled “A 10 Gb/s CMOS Clock and Data Recovery Circuit with Frequency Detection”, ISSC Digest of Technical Papers, pp.78-79, February 2001 by J. Savoj and B. Razavi, a conventional half-rate CDR circuit includes a half-rate phase and frequency detector for outputting a full-rate retimed signal, a charge pump circuit, a low-pass filter (LPF) and a voltage controlled oscillator (VCO) for outputting a half-rate clock.
In another known CDR circuit described in Japanese Patent Laid-Open Publication No. 2002-359555, when phase of a clock generated by a VCO lags behind that of input data, a phase detector outputs a pump-up signal so as to raise frequency of the output clock of the VCO. On the other hand, when phase of the clock generated by the VCO goes ahead of that of the input data, the phase detector outputs a pump-down signal so as to lower frequency of the output clock of the VCO.
In the prior art half-rate CDR circuits, since a half-rate phase detector does not have phase comparison polarity suitable for use in an N type VCO of low jitter, a P type VCO having poor jitter characteristics should be employed in many cases. Thus, in the prior art half-rate CDR circuits, such a problem arises that operating margin is insufficient due to increase of jitter of the feedback clock oscillated by the VCO.
Meanwhile, in case the N type VCO of low jitter is used in the prior art half-rate CDR circuits, such disadvantages are incurred that circuit configuration of the half-rate phase detector becomes complicated and circuit scale of the half-rate phase detector, namely, power consumption also becomes large.
Furthermore, the prior art half-rate CDR circuits have such an inconvenience that its delay amount cannot be adjusted from, outside.